1. Field of the Invention
The present invention relates to an integrated device with pads. More specifically, the invention relates to utilizing capacitances formed within the device beneath the pads.
2. Discussion of the Related Art
As is known, integrated circuits within a device are connected electrically to the outside of the device by means of pads. The pads are exposed metal regions, surrounded by insulating material and connected electrically to the input and output components of the device to permit connection of the components to respective pins by means of respective bonding wires.
The various superimposed layers of insulating and conductive material formed on a substrate and forming the device itself normally extend beneath the pad so that the upper surface of the device is flat.
FIG. 1 illustrates a known structure of the device region beneath the pads. FIG. 1 shows a vertical section of an integrated device 1 comprising a substrate 2 of P-type semiconductor material (typically silicon) on which are superimposed: a first dielectric layer 6 forming a field oxide layer; a first conductive layer 7 of polycrystalline silicon, typically used to form the gate regions of the components; a second dielectric layer 8, preferably of silicon oxide; a second conductive layer 9 of metal material to form the first metal level; a conductive portion 10 of metal material (so-called "vias") surrounded by an insulating layer 13; a third conductive layer 11 of metal material to form the second metal level; and a surface layer 12 of passivation oxide. Conductive portion 10 electrically connects second conductive layer 9 to third conductive layer 11--which are otherwise mutually insulated--to permit external connection of the first metal level.
As shown in FIG. 1, third conductive layer 11 forms a pad 14 not covered by passivation oxide layer 12 for bonding a respective bonding wire (not shown).
The presence of alternating conductive and dielectric layers inside the device results in a series of parasitic capacitors. In particular, a first capacitor 17 between first conductive layer 7 and second conductive layer 9; and a second capacitor 18 between first conductive layer 7 and substrate 2, and in series with first capacitor 17.
Since, in known devices, such parasitic capacitors inside the integrated device are undesirable, the device is designed to minimize their capacitance. Nevertheless, the need for a pad large enough to ensure reliable bonding of the external metal wires, and the necessity for a number of superimposed layers to ensure the device is flat, impose a total capacitance of no less than about 0.35 pF.
On the other hand, in the prior art, the capacitance obtainable is never significant enough for the parasitic capacitors to be used advantageously within the integrated device.